Designing and fabricating electronic systems typically involves many steps, known as a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system. The design flow typically starts with a specification for a new circuit, which can be transformed into a logical design. The logical design can model the circuit at a register transfer level (RTL), which is usually coded in a Hardware Description Language (HDL), such as System Verilog, Very high speed integrated circuit Hardware Description Language (VHDL), System C, or the like.
The logical design can be functionally verified, for example, utilizing a design verification tool, which can simulate the functionality of the logical design in response to various test stimulus. The design verification tool also may simulate a test bench, which can generate different test stimulus and provide the test stimulus to the simulated logical design. The design verification tool can record signal states and transitions of the simulated logical design, often called waveform data, which can be analyzed to determine whether the logical design operated differently than expected in response to the test stimulus. When the output from the simulated logical design was different than expected, a designer can review in an attempt to identify a “bug” in the logical design. When the “bug” is located and fixed, or the logical design is otherwise modified, the functional verification process can restart, sometimes to re-verify the entire logical design.
The design verification tool also can record coverage events that occurred during simulation with the test bench, which can identify how well the test stimulus exercised the functionality of the logical design. The designer can review the recorded coverage events to identify holes or gaps in coverage for the test bench, and generate new test benches that can attempt to exercise the functionality in the logical design differently to fill the holes or gaps in the coverage. Both debugging and coverage can motivate designers to undergo the time-consuming process of iteratively simulating the logical design with different test stimulus before considering the logical design functionally verified.